In U.S. Pat. No. 8,212,283 B2 a prior art reverse-conducting insulated gate bipolar transistor (RC-IGBT) in form of a Bi-mode Insulated Gate Transistor (BIGT) as described (shown in FIG. 1), which comprises a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer 100, part of which wafer forms an (n−) doped base layer 101 with a first doping concentration and a base layer thickness 102. The RC-IGBT comprises a collector side 103 and an emitter side 104, whereas the collector side 103 is arranged opposite of the emitter side 104 of the wafer 100.
The base layer thickness 102 is the maximum vertical distance between the collector and emitter side 103 and 104 of that part of the wafer 100 with the first doping concentration.
An n doped cathode layer 1 of higher doping concentration than the first doping concentration and a p doped anode layer 2 are alternately arranged on the collector side 103. The cathode layer 1 comprises at least one or a plurality of first regions 10, wherein each first region 10 has a first region width 11.
The anode layer 2 comprises at least one or a plurality of second regions 20 and at least one or a plurality of pilot regions 22, wherein each second region 20 has a second region width 21 and each pilot region 22 has a pilot region width 23.
Any region (first, second or pilot region) has a region width and a region area, which is surrounded by a region border.
In an exemplary embodiment, a shortest distance is the minimum length between a point within said region area and a point on said region border. In that exemplary embodiment, each region width is defined as two times the maximum value of any shortest distance within said region.
An n doped source region 3, a p doped well layer 4 and a gate electrode having an electrically conductive gate layer 5 and an insulating layer 6, which insulates the gate layer 5 from any doped layer and an emitter electrode 8, are arranged at the emitter side 104.
The reverse-conducting semiconductor device comprises an active region 110, which is an area in the wafer 100, which includes and is arranged below any of the source region 3, well layer 4 or gate layer 5.
The following geometrical rules have to be fulfilled:                each pilot region area is a p doped area, in which a maximum value of all shortest distances to any border point is bigger than the base layer thickness 102,        the at least one pilot region 22 is arranged in the central part of the active region 110 in such a way that there is a minimum distance between the pilot region border to the active region border of at least one time the base layer thickness 102,        at least one second region 20 is that part of the anode layer 2, which is not the at least one pilot region 22,        the total area (sum of the areas) of the at least one pilot region 22 is between 10 and 30% of the active region 110,        each first region width 11 is smaller than the base layer thickness 102.        
The pilot region 22 represents a pilot IGBT region, which eliminates snap-back effects at low currents. The snap-back effect of a BIGT depends on the resistance of the base layer, which in turn depends on the resistivity and thickness of the base layer 102. For devices having a greater base layer thickness 102, the voltage drop across the base layer is larger. Therefore, also the total on-state voltage drop is higher for such devices, and snap-back effect occurs at higher voltages.
The introduction of a sufficiently large p doped region (pilot region) can avoid such snap-back effect in a high voltage IGBT device. A minimum distance between this pilot region 22 and the border of the active region 110 is essential for good thermal performance and improvement of the device SOA since the pilot IGBT does not include transition parts of the chip such as those from active to termination regions 111. Furthermore, by using a pilot region 22, snap-back behaviour is improved compared to distributed smaller pilot regions.
By introducing a larger pilot region 22 compared to the smaller second regions 20, large areas of the device with shorted structures are maintained. By the introduction of the pilot region 22 with much increased dimensions compared to the first and second regions 10, 20, a region is created which is dedicated solely as IGBT region and not operating in the diode mode. The p-type pilot region 22 ensures increased IGBT area. The pilot region 22 is mainly present to give more freedom to determine the IGBT to diode area ratio and decouple this design aspect from the standard approach involving the small second regions 22 only.
The pilot region 22 is surrounded by shorted regions with alternating first and second doped regions 10, 20 (mixed region). Since the small first and second regions 10, 20 do not heavily influence the IGBT snap-back mode in line with the above design rule, their dimensions are adjusted to achieve the required diode area.
The first and second regions 10, 20 form the main shorted region in which the silicon area included is utilized in both IGBT and diode mode. These regions also influence the main IGBT electrical properties.
However, prior art RC-IGBTs have a snap-back in their on-state characteristics as a result of anode shorting. In the case of the prior art BIGT the initial snap-back is minimized or even removed by providing a large pilot region 22 in the center of the device. Consequently the injected carrier distribution becomes uneven in the BIGT having a wide anode in the pilot area and a strongly shorted anode in the mixed region.
During the IGBT mode conduction, the carrier plasma has its highest density in the active region 110 above the middle of the projection of the pilot region 22. As a result, during IGBT-mode conduction the temperature at the center of the chip is increased compared to what is normally seen in prior art IGBTs. Therefore, during the IGBT-mode turn-off the dynamic avalanche sets early at the cells located above the center of the widest/largest anode area, which is the pilot-IGBT region 22. This effect is mainly pronounced when the plasma is inhomogeneously distributed between the pilot-IGBT region 22 and the shorted region 10, 20. This happens mainly at lower temperatures (room temperature) and low currents up to the nominal current. The dynamic avalanche contributes to the increased turn-off losses during these conditions and creates concerns regarding the reliability of the component continuously operating in dynamic avalanche mode. The effect becomes gradually less as the current increases and the shorted regions 10,20 are flooded with carriers, but nevertheless the maximum turn-off capability of the BIGT is reduced compared to a corresponding prior art RC-IGBT.
FIGS. 20 and 21 show the carrier plasma (hole density) concentration in a semiconductor device in a plane located 5 μm from the emitter during IGBT mode turn-off. The hole density is shown at three different voltages of 500 V, 1200 V and 1900 V. FIG. 20 shows the hole density for a prior art BIGT structure, and on the right side a prior art RC IGBT structure is shown.
In the prior art BIGT structure (FIG. 20) dynamic avalanche occurs (seen as a filament of high plasma concentration) in the middle of the Pilot region (at the position −250 μm). The RC IGBT without a pilot-IGBT region as shown in FIG. 21 shows a smoother behavior without dynamic avalanche.
FIG. 22 shows an example of a prior art BIGT turn-off waveform showing the onset of dynamic avalanche detected as the change (slowing down) of the dV/dt rate.